1. Field of the Invention
The present invention relates to a direct memory access (DMA) transfer apparatus configured to sequentially read, into a register, at least one transfer setting value for data transfer stored in a memory and to perform DMA transfer processing based on the read transfer setting value, a data transfer control method using the DMA transfer apparatus, and a data transfer control program using the DMA transfer apparatus.
2. Description of the Related Art
A conventional method uses data transfer hardware, such as a DMA controller, during processing for converting input data described based on a specific data format into another data format.
Such data transfer hardware is used when decoded data obtained based on received coded or encrypted data is used for specific processing, such as print processing or display processing.
In particular, a conventional printing apparatus prints out decoded image data obtained based on received coded and compressed image data. In the case of using an inkjet type printer (hereinafter simply referred to as a “printer”) that performs processing on print data including line-sequential raster data, a host computer sequentially sends data coded and compressed for each line.
Conventional data transfer hardware, particularly, conventional DMA transfer hardware, sequentially loads, on a register, transfer setting values (hereinafter referred to as a “descriptor”) for a plurality of transfer operations, which are appropriately stored in a memory to perform data transfer, as discussed in Japanese Patent Application Laid-Open No. 07-21117. Such a DMA transfer mode is called an “array chain transfer mode” or a “link array chain transfer mode”.
In many cases, print data from a host computer may have different data length line by line after decoding processing. In particular, in the case of Run Length Encoding (RLE), such as PackBits Encoding or Seed Row Encoding, the data length after decoding may be known only after performing decoding processing.
In conventional processes, one way to unify the length of the lines is to set a width of a paper sheet (sheet of a document to be read) as the decoded data buffer length. In this regard, however, it is more useful not to access the memory with regard to the portion of the sheet having no images during image processing. Furthermore, it increases the number of accesses to the memory to fixedly set the data length for the width of the sheet as the decoded data buffer length, which is not useful in terms of processing efficiency.
In this regard, another conventional method predicts a necessary minimum decoded data buffer length and sets a descriptor for one band to perform decoding. If the predicted necessary minimum decoded data buffer length is different from an actual decoded data length, particularly, if the actual decoded data length is longer than the decoded data buffer length, the decoded data is segmented or cut at the length equivalent to the decoded data buffer length. In this case, the CPU re-generates an appropriate descriptor with an elongated decoded data buffer length, and the decoder performs decoding again.
In this regard, Japanese Patent Application Laid-Open No. 06-103181 discusses a method in which, when a failure, such as a transmission failure, has occurred, a sending unit notifies an abort notification signal to the DMA controller. In this method, the DMA controller, after receiving the notification, automatically resumes data transfer.
Meanwhile, a few restrictions exist for a DMA controller or a decoder to reduce the number of gates in the electronic circuits and the cost of manufacturing thereof. For example, a minimum value that can be set as the transfer byte length is restricted.
In the case where it is necessary to process data smaller than the minimum value, the CPU performs the necessary processing. For example, in the case where it is necessary for the CPU to decode Seed Row-coded N-th line data, the CPU can decode the N-th line data only after (N−1)-th line data has been completely decoded.
In this case, the CPU once executes a descriptor including the setting for the decoding processing for up to the (N−1)-th line data, decodes the N-th line data, and provides the (N+1)-th line and subsequent data with a new descriptor.
However, in the case of performing the decoding processing again as described above, it is necessary to generate the settings for the data to be coded with the CPU and to manage the generated settings on the memory, although the setting for the hardware can be stored in the memory as a descriptor. That is, it is necessary, in this case, to generate separate setting data and to manage the generated setting data with respect to the decoding processing to be performed with the DMA controller or the decoder and to the decoding processing to be performed with the CPU.
Furthermore, if the data decoded with the CPU can be processed with the hardware, it is necessary to generate a new descriptor. As described above, in a conventional method, it is necessary for the CPU to perform complicated processing, due to the restriction as to the minimum value that can be set on the DMA controller or the decoder as the transfer byte length.